1. Field of the Invention
The present invention relates to a semiconductor memory device called an SRAM using a (thin film transistor) load.
2. Description of the Prior Art
An SRAM using a TFT load is obtained by substituting a PMOS-TFT for a resistor element in an SRAM that uses a resistor load. The SRAM using a TFT load has an advantage in that resistance to a soft error can be improved by obtaining a large ON current with a TFT.
FIG. 1 shows an SRAM using a TFT load, according to the prior art. In this prior art SRAM, an active layer of load PMOS transistors 12 of each of memory cells 11 is formed by a polysilicon layer 13. The polysilicon layer 13 continues on to the PMOS transistors 12 of each of the memory cells 11 and extends across blocks of a memory cell array.
At an end portion of the block of the memory cell array, the polysilicon layer 13 is connected to an Al layer 15 directly or through another polysilicon layer 14 doped with a p-type impurity at a high concentration or an impurity diffusion layer (not shown) of a semiconductor substrate. Therefore, in this prior art SRAM, the polysilicon layer 13 and the Al layer 15 serve as a power supply line. Note that one block of a memory cell array is constituted by, e.g., 128 cells.
A polycide layer 17 is connected to driver NMOS transistors 16 of each of the memory cells 11, and the polycide layer 17 is connected to Al layers 18 16 bits (i.e., 16 cells). Therefore, in this prior art SRAM, the polycide layer 17 and the Al layer 18 serve as a ground line.
The gate electrodes of transfer NMOS transistors 21 of each of the memory cells 11 serve as a word line 22, and a pair of noninverted and inverted bit lines 23 are connected to the NMOS transistors 21, respectively.
As is apparent from FIG. 1, the polysilicon layer 13 and the polycide layer 17 generally extend in a direction parallel to the word line 22, and the Al layers 15 and 18 and the bit lines 23 generally extend perpendicularly to the word line 22.
FIG. 2 shows another prior art SRAM using a TFT load. This prior art SRAM has the same arrangement as that of FIG. 1 except that Al layers 15 are not only arranged at the end portion of a memory cell array but connected to the polysilicon layer 13 at intervals of, for example 16 bits together with Al layers 18.
In the SRAM using a TFT load, the polysilicon layer 13 is formed by a thin film having a thickness of about 100 to 500 .ANG. such that an OFF current of the PMOS transistor 12 serving as a TFT is decreased so that the ON/OFF current ratio is increased and the data retention characteristics of the memory cells 11 are improved.
In addition, the dose of a p-type impurity for forming the source/drain region of the polysilicon layer 13 is suppressed to be as low as 10.sup.14 cm.sup.-2 such that lateral diffusion of the source/drain region of the PMOS transistor 12 is decreased to obtain a desired channel length.
For this reason, the sheet resistance of the polysilicon layer 13 is high, i.e., about 100 k.OMEGA.. Therefore, as in the prior art SCRAM B shown in FIG. 1, when the Al layer 15 is arranged only at the end portion of the memory cell array, the power supply line constituted by the polysilicon layer 13 and the Al layer 15 have a high resistance, and the ON current of the PMOS transistor 12 is decreased.
In contrast to this, as in the prior art SRAM shown in FIG. 2, since the Al layers 15 are arranged every 16 bits, the resistance of the power supply line is lower than that of the prior art SRAM of FIG. 1.
In the prior art, SRAM of FIG. 2, however, the area required for arranging the Al layers 15 is larger than that of the prior art SRAM of FIG. 1 and the degree of integration is decreased. Even when the Al layer 15 is to be formed by an Al layer which is an upper layer of the Al layer 18, since the Al layer has poor step coverage, the Al layer 15 must be temporarily connected to the polysilicon layer 13 through the same layer as the Al layer 18, and the degree of integration is inevitably decreased.